Register Set with common ALU

Register Set with common ALU

• By choosing the different components in the system, the control unit that controls the CPU bus system guides the information flow through the registers and ALU. To do the procedure R1 + R2 + R3.

The control must provide binary selection variables to the following selector inputs:

1. MUX A selector (SELA): To place the content of R2 into bus A.
2. MUX B selector (SELB): To place the content o f R 3 into bus B.
3. ALU operation selector (OPR): To provide the arithmetic addition A + B.
4. Decoder destination selector (SELD): To transfer the content of the output bus into R1.

• The control unit generates the four control selection variables, which must be accessible at the start of a clock cycle.
• During the clock cycle interval, data from the two source registers propagates through the gates of the multiplexers and the ALU, to the output bus, and into the inputs of the destination register.
• The binary information from the output bus is then transferred into R1 when the next clock transition occurs.
• The ALU is built with high-speed circuits to provide a quick reaction time.

Control Word

• The unit has 14 binary selection inputs, each of which defines a control word when their values are added together. Figure 2 shows the 14-bit control word (b).
• There are four fields in all. Each of the three fields has three bits, while one field has five bits.
• The three bits of SELA are used to pick a source register for the ALU's A input. The three bits of SELB are used to choose a register for the ALU's B input.
• Using the decoder's seven load outputs, the three bits of SELD choose a destination register.
• The five bits of OPR are used to pick one of the ALU's operations.
• When applied to the selection inputs, the 14-bit control word specifies a specific micro operation.

Control Word

• The binary code for each of the three fields is specified by the 3-bit binary code stated in the table's first column.
• The register chosen by fields SELA, SELB, and SELD is the one whose decimal number equals the code's binary number. When SELA or SELB is set to 000, the external input data is selected by the appropriate multiplexer.
• No destination register is selected when SELD = 000, however the contents of the output bus are available in the external output. The ALU is a computer that performs arithmetic and logic operations.
• Furthermore, the CPU must do shift operations. The shifter can be connected to the ALU's input to give preshifting capabilities or to the ALU's output to provide postshifting capacity. The shift operations are sometimes incorporated with the ALU.
• Table 8 shows the function table for this ALU. Table 2 specifies the encoding of ALU operations for the CPU. Each operation is given a symbolic name in the OPR field, which contains five bits.

Encoding of ALU Operations