General Register Organization

During multiplication, memory spaces are required for storing pointers, counters, return addresses, temporary results, and partial products.
Because memory access is the most time-consuming activity in a computer, having to refer to memory locations for such applications is time-consuming.
Keeping these intermediate values in CPU registers is more convenient and efficient.
When the CPU contains a high number of registers, it is most economical to connect them via a common bus system.
Not just for direct data transfers, but also for conducting different micro operations, the registers connect with one another.

General Register Organization

As a result, a single unit must be provided that can do all of the processor's arithmetic, logic, and shift micro operations.
Above fig. depicts the bus structure for seven CPU registers. To construct the two buses A and B, the output of each register is linked to two multiplexers (MUX). Each multiplexer's selection lines choose one register or the input data for that bus.
The inputs to a shared arithmetic logic unit are formed by the A and B buses (ALU).
The arithmetic or logic micro-operation to be executed is determined by the operation selected in the ALU.
The micro operation's result is accessible for output data and also goes into all of the registers' inputs.
A decoder selects the register that gets information from the output bus.
The decoder activates one of the register fill inputs, creating a connection between the data on the output bus and the destination register's inputs.